In the technical field of the MOS transistors, so called LDD (Lightly Doped Drain) structure is well known as a useful way to weaken concentration of the electric field between the drain areas and the gate areas. In the LDD structure, between the gate areas and the drain areas of heavily doped regions near the surface of the substrate, a lightly doped region of the same conductive type as the heavily doped region formed which causes a reduction of the strength of the electric field there. This LDD structure will be described referring to a figure.
Referring to FIG. 4(a), an active region is defined on the silicon semiconductor substrate 21 by forming field oxide layers 22 by way of an isolation process so called LOCOS. In the active region, a silicon oxide layer and a polysilicon layer are formed on the surface of the substrate successively, and a photoresist layer 28 is formed on the polysilicon layer and patterned by a conventional technique of the photo-lithography. Then an unisotropic dry etching is performed on the whole surface using the photo-resist layer 28 as an etching mask to form a gate oxide layer 23 of the silicon oxide and a gate electrode 24 of the polysilicon.
After the patterned resist layer 28 is removed from the surface of the gate electrode 24, an ion injection of phosphorus is performed by using the gate electrode 24 as a mask to form shallow surface region in which phosphorus is slightly doped.
A silicon oxide layer of a thickness of about 2000 .ANG. is formed on the whole surface including active regions using a conventional technique of the chemical vapor deposition (CVD). Side walls 25 of the silicon oxide are formed at the side portions of the gate electrode 24 in a manner of self-alignment as shown in FIG. 4(c), by performing unisotropic etching. A width of the side walls 25 will be made to be less than 0.2 micron for LDD structures under the submicron design rule.
An ion injection of arsenic (As) is performed to form the heavily doped region under the surface of the active region by using the gate electrode 24 and side walls 25 as shielding masks. In this case, arsenic is injected in the areas which are apart from the gate electrode 24 by the width of the side walls 25. An annealing process is performed to activate the lightly doped regions 26 and the heavily doped regions 27 to accomplish the whole process to fabricate a MOS transistor having the LDD structure.
In the process for fabricating the MOS transistor having the LDD structure described above, ion injection processes are performed twice for forming the lightly doped regions 26 and the heavily doped regions 27 respectively. And between the two ion injection processes, the process for forming the side walls 25 must be performed including a formation of the silicon oxide layer to be changed into the side walls though the unisotropic etching.
As a result, the number of processes required becomes large to cause increase of the fabrication cost and decrease of the yield and the reliability.